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65 com / 132 seg driver & controller for stn lcd july. 1999. ver. 1.3 prepared by: tae- kwang, park parktk@samsung.co.kr ks00 40 contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
ks00 40 65 com / 132 seg driver & controller for stn lcd 2 ks00 40 specification revision history version content date 0.0 original mar. 199 8 1.0 1) changed function mpu interface pin & method are changed. ddram extended style is changed from horizontal to vertical. reference voltage can be selected between internal v ref and v dd by ref pin. 2) removed function horizontal display shift function is removed. 3) added function double height character display function center mode display function cgram full graphic function line cursor function vertical shift by character & first line fix and vertical shift function 4-bit interface mode 4) changed pin name dt1 ? dummy (not connected) dt0 ? ref (reference voltage selection) dirc ? mi (6800- / 8080-series selection) dirs ? if (8- / 4- bit interface length selection) res ? reset (h/w reset) rw ? rw_wr (read / write selection in 6800-series, write enable in 8080-series) e ? e_rd (read / write enable in 6800-series, read enable in 8080-series) coms1, 2 ? comi1, 2 (common icon) segs1 ~ segs4 ? segi1 ~ segi4 (segment icons) jun. 199 8 1.1 1 ) changed pin name vc5on ? test3 ( connect to vss ) tmps0 ? test4 ( connect to vss) tmps1 ? test5 ( connect to vss) 2) dc spec changed idd (3v): 150 m a max . ? 180 m a max . idd (5v): 250 m a max . ? 280 m a max . 3) p ower on / off sequence is a dded. apr.1999 1. 2 page 1, 3, 23: cgrom character size is changed from 8,192 to 8,160. page 63, 64: v ref item, ref = h ? ref = l jun .1999 1.3 page 6 : x-coordinates are changed (pad no.206 to 246) jul .1999
65 com / 132 seg driver & controller for stn lcd ks00 40 3 co ntents introduction ................................ ................................ ................................ ................................ ......... 1 features ................................ ................................ ................................ ................................ ................. 1 block diagram ................................ ................................ ................................ ................................ ...... 3 pad configuration ................................ ................................ ................................ .............................. 4 pad center coordinates ................................ ................................ ................................ ................... 5 pin description ................................ ................................ ................................ ................................ ..... 8 power supply ................................ ................................ ................................ ................................ . 8 lcd driver supply ................................ ................................ ................................ ......................... 8 system control ................................ ................................ ................................ ............................ 9 mpu interface ................................ ................................ ................................ ................................ 9 lcd driver output ................................ ................................ ................................ ....................... 10 test pin ................................ ................................ ................................ ................................ ............ 10 function description ................................ ................................ ................................ ........................ 11 system interface ................................ ................................ ................................ ......................... 11 ram map ................................ ................................ ................................ ................................ ........... 14 character generator rom for a full-size font (fcgrom) ................................ ........... 23 character generator rom for a half-size font (hcgrom) ................................ .......... 23 low power consumption mode ................................ ................................ ............................... 26 lcd driving circuit ................................ ................................ ................................ ...................... 26 display shift control ................................ ................................ ................................ ................ 27 instruction description ................................ ................................ ................................ ................... 28 initializing & power save mode setup ................................ ................................ .......................... 40 hardware reset ................................ ................................ ................................ ........................... 40 initializing by instruction ................................ ................................ ................................ ........ 42 sleep mode set or release by instruction ................................ ................................ ........ 43 recommendation of power on / off sequence ................................ ................................ . 44 lcd driving power supply circuit ................................ ................................ ................................ 45 voltage converter ................................ ................................ ................................ .................... 46 voltage regulator ................................ ................................ ................................ ..................... 48 lcd bias resistor & follower ................................ ................................ ................................ . 52 use the external power supply ................................ ................................ ............................ 53 application information ................................ ................................ ................................ .................. 54 mpu interface method ................................ ................................ ................................ ............... 54 lcd panel connection method (1/65 duty configuration) ................................ ............. 56 frame frequency ................................ ................................ ................................ ................................ 60 maximum absolute rate ................................ ................................ ................................ .................... 63 electrical characteristics ................................ ................................ ................................ ........... 64 dc characteristics ................................ ................................ ................................ ..................... 64 ac characteristics ................................ ................................ ................................ ..................... 66
65 com / 132 seg driver & controller for stn lcd ks00 40 1 introduction the KS0040 is a lcd driver and controller lsi for liquid crystal dot matrix character display systems. it can display 1 to 4 lines of 8 characters with 16 x 16 dots format. so it is suitable for display of asian characters such as korean, chinese and japanese. also 8 x 16 dot half size alphanumeric characters can be displayed. and it can display 64 x 128 dots graphic lcd using internal cgram. voltage converter (2 to 4 times), voltage regulator and voltage follower & bias circuit s are built in the ic. features driver output circuits - common outputs: 64 common + 1 common for icon - segment outputs: 128 segment + 4 segment for icon applicable duty ratios display size duty contents of outputs 1 - line x 8 characters 1/17 1 x 8 characters + 16 x 4 vertical icons + 128 horizontal icons 2 - line x 8 characters 1/33 2 x 8 characters + 32 x 4 vertical icons + 128 horizontal icons 3 -l ine x 8 characters 1/49 3 x 8 characters + 48 x 4 vertical icons + 128 horizontal icons 4 - line x 8 characters 1/65 4 x 8 characters + 64 x 4 vertical icons + 128 horizontal icons on-chip display data ram - full-size character generator rom (fcgrom): 2,088,960 bits (8,160 characters x 16 x 16 dot) - half-size character generator rom (hcgrom): 16,384 bits (128 characters x 8 x 16 dot) - character generator ram (cgram): 8,192 bits (32 characters x 16 x 16 dot) - display data ram (ddram): 1,024 bits (64 characters x 2 byte) - icon ram (iconram): 384 bits (128 horizontal icons + 64 x 4 vertical icons) microprocessor interface - 8- / 4- bit parallel interface mode: 6800-series, 8080-series - serial interface mode: 4 pin s clock synchronous serial interface function set - various instruction sets: vertical dot-by-dot display shift, double height character, power control , etc. - com / seg bi-directional - h /w reset on-chip analog circuit - automatically adjusted oscillator circuit by duty set - electrical volume for contrast control (64 steps) - voltage converter (2 to 4 times) / voltage regulator ( t emperature coefficient = -0.05%/ o c ) / voltage follower & bias circuit operating voltage range - supply voltage (v dd ): 2.4 to 5.5v - lcd driving voltage (v lcd = v0 - v ss ) = 13.0v
ks00 40 65 com / 132 seg driver & controller for stn lcd 2 low power consumption - sleep mode operation ( v dd = 3v: 5ua m ax .) - normal mode operation ( v dd = 3v, v0 = 9v: 1 5 0ua t yp .) package type - gold bumped chip or tcp
65 com / 132 seg driver & controller for stn lcd ks 00 40 3 block diagram system interface 4 bit/8 bit serial interface i/o buffer instruction register (ir) instruction decoder address counter display data ram (ddram) 128x8 bits data register (dr) 8 character generator ram (cgram) 1,024 bytes character generator rom for half size char. font (hcgrom) 16,384 bits cursor blink control common driver 65 bits shift register ( bi-dir) segment driver 128-bits latch circuit ( bi-dir) 128-bits shift register lcd driver voltage selector parallel to serial converter & scroll control circuit lcd driving power circuit voltage converter voltage regulator voltage follower & bias resistor timing generator oscillator com1 to com64 comi1 comi2 csb rs rw_wr e_rd db7 (si) db6 (scl) db5 to db4 db3 to db0 reset ps mi if ck v dd v ss character generator rom for full size char. font (fcgrom) 2,088,960bit address generator display attribute control circuit 4 bits latch circuit 13 7 3 4 8 8 16 16 8 16 8 v4 v3 v2 v1 v0 vr ref v out cap3- cap3+ cap2- cap2+ cap1- cap1+ 8 8 8 seg1 to seg128 segi1 segi2 segi3 segi4 icon ram (iconram) 48 bytes figure 1. block diagram
ks00 40 65 com / 132 seg driver & controller for stn lcd 4 pad configuration ? .. ....................... ............ . x y (0,0) dummy pad 1 298 299 335 118 117 154 KS0040 15 5 figure 2. pad configuration table 1 . ks00 40 pad dimensions size item pad no. x y unit chip size - 12160 3860 1 to 117 90 pad pitch 118 to 335 70 1 to 117 56 114 118 to 154 108 50 155 to 298 50 108 bumped pad size 229 to 335 108 50 bumped pad height 1 to 138 1 7 ( typ.) m m cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (-5886.5, - 1558) 30 m m 30 m m 30 m m (+5886.5, - 1543) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-5738, +1800) (+5738, +1800) 42 m m 108 m m
65 com / 132 seg driver & controller for stn lcd ks00 40 5 pad center coordinates table 2. pad center coordinates [unit: m m ] coordinate coordinate coordinate pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 dummy dummy vss test1 vdd dummy vss ref vdd mi vss if vdd ps vss csb vdd reset rs rw_wr e_rd db7 db6 db5 db4 db3 db2 db1 db0 dummy dummy dummy vss vss vss vss vss vss vss vss vss -5220 -5130 -5040 -4950 -4860 -4770 -4680 -4590 -4500 -4410 -4320 -4230 -4140 -4050 -3960 -3870 -3780 -3690 -3600 -3510 -3420 -3330 -3240 -3150 -3060 -2970 -2880 -2790 -2700 -2610 -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620- -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 vss dummy vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd dummy vout vout vout vout dummy cap3+ cap3+ cap3+ cap3+ cap3- cap3- cap3- cap3- cap1+ cap1+ cap1+ cap1+ cap1- cap1- cap1- cap1- cap2+ cap2+ cap2+ cap2+ cap2- cap2- cap2- -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 -270 -180 -90 0 90 180 270 360 450 540 630 720 810 900 990 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 cap2- dummy dummy vr vr vr vr dummy v0 v0 v0 v0 dummy v1 v1 v2 v2 v3 v3 v4 v4 dummy vss test3 vdd test 5 vss test 4 vdd test2 vss ck vdd dummy dummy dummy comi1 com1 com2 com3 com4 2160 2250 2340 2430 2520 2610 2700 2790 2880 2970 3060 3150 3240 3330 3420 3510 3600 3690 3780 3870 3960 4050 4140 4230 4320 4410 4500 4590 4680 4770 4860 4950 5040 5130 5220 5920 5920 5920 5920 5920 5920 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1806 -1326 -1256 -1186 -1116 -1046 -976
ks00 40 65 com / 132 seg driver & controller for stn lcd 6 table 2. pad center coordinates (continued) [unit: m m ] coordinate coordinate coordinate pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 com33 com34 com35 com36 com37 com38 com39 com40 com49 com50 com51 com52 com53 com54 com55 com56 segi1 segi2 dummy dummy dummy dummy dummy dummy dummy dummy dummy seg1 seg2 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5920 5005 4935 4865 4795 4725 4655 4585 4515 4445 4375 -906 -836 -766 -696 -626 -556 -486 -416 -346 -276 -206 -136 -66 4 74 144 214 284 354 424 494 564 634 704 774 844 914 984 1054 1124 1194 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 16 5 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 seg 3 seg 4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 4 305 4 235 4165 4095 4025 3955 3885 3815 3745 3675 3605 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770
65 com / 132 seg driver & controller for stn lcd ks00 40 7 table 2. pad location (continued) [unit: m m ] coordinate coordinate coordinate pad no. pad n ame x y pad no. pad n ame x y pad no. pad n ame x y 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 seg114 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 dummy dummy dummy dummy dummy dummy dummy dummy dummy segi3 segi4 comi2 com64 com63 com62 com61 -3535 -3605 -3675 -3745 -3815 -3885 -3955 -4025 -4095 -4165 -4235 -4305 -4375 -4445 -4515 -4585 -4655 -4725 -4795 -4865 -4935 -5005 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1770 1194 1124 1054 984 914 844 774 704 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 com60 com59 com58 com57 com48 com47 com46 com45 com44 com43 com42 com41 com32 com31 com30 com29 com28 com27 com26 com25 com16 com15 com14 com13 com12 com11 com10 com9 dummy -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 -5920 634 564 494 424 354 284 214 144 74 4 -66 -136 -206 -276 -346 -416 -486 -556 -626 -696 -766 -836 -906 -976 -1046 -1116 -1186 -1256 -1326
ks00 40 65 com / 132 seg driver & controller for stn lcd 8 pin description power supply table 3 . pin description name i/o description vdd power supply connect to mpu power supply pin vss power 0v (gnd) bias voltage level for lcd driving voltages have the following relationship: v0 3 v1 3 v2 3 v3 3 v4 3 vss when the on-chip power circuit is active, these voltages are generated according to the state of lcd bias, as following table. lcd bias v1 v2 v3 v4 1/9 bias (8/9) x v0 (7/9) x v0 (2/9) x v0 (1/9) x v0 1/8 bias (7/8) x v0 (6/8) x v0 (2/8) x v0 (1/8) x v0 1/7 bias (6/7) x v0 (5/7) x v0 (2/7) x v0 (1/7) x v0 1/5 bias (4/5) x v0 (3/5) x v0 (2/5) x v0 (1/5) x v0 v0 v1 v2 v3 v4 i/o lcd driver supply table 3 . pin description (continued) name i/o description cap1+ capacitor1+ connect for the internal voltage converter cap1- capacitor1- connect for the internal voltage converter cap2+ capacitor2+ connect for the internal voltage converter cap2- capacitor2- connect for the internal voltage converter cap3+ capacitor3+ connect for the internal voltage converter cap3- o capacitor3- connect for the internal voltage converter v out i/o voltage converter output vr i v0 voltage adjustment pin which is valid only when using external resistors ref i select the reference voltage of internal voltage regulator ref = "high": the reference voltage of internal voltage regulator is the voltage of v dd . ref = "low": the reference voltage of internal voltage regulator is the internal v ref (2.0v).
65 com / 132 seg driver & controller for stn lcd ks00 40 9 system control table 3 . pin description (continued) name i/o description ck i external clock input it must be fixed to "high" or ?low? when the internal oscillation circuit is used. in case of external clock mode, used as the clock input and osc bit should be off. mi i select the kinds of the mpu to interface when mi = "high": 6800-series mpu interface mode when mi = "low": 8080-series mpu interface if i select the interface bit length when parallel interfacing (ps = "high") when if = "high": 8-bit interface mode when if = "low": 4-bit interface mode ps i select interface mode with the mpu when ps = "high": parallel interface mode when ps = "low": serial interface mode mpu interface table 3 . pin description (continued) name i/o description reset i hardware reset input initialization is performed by edge sensing (rising or falling) of the reset signal. csb i used as chip selection input when csb = "high", not selected when csb = "low", selected rs i used as register selection input when rs = "high", data register when rs = "low", instruction register rw_w r i when mi = "high"(6800-series mpu interfacing), used as read (rw_wr = "high") / write (rw_wr = "low") selection input (r/w). when mi = "low "(8080-series mpu interfacing), used as write enable input (wr). e_rd i when mi = "high"(6800-series mpu interfacing), used as read/write enable input (e). when mi = "low "(8080-series mpu interfacing), used as read enable input (rd). db0 to db7 i/o when 8-bit interface mode, db0 to db7 are used as bi-directional data bus pin. when 4-bit interface mode, only db4 to db7 are used as data input pin and db0 to db3 are not used. when serial mode, db6 (scl) is used as serial clock input pin, db7 (si) is used as serial data input pin and the others are not used.
ks00 40 65 com / 132 seg driver & controller for stn lcd 10 lcd driver output table 3 . pin description (continued) name i/o description com1 to com64 o common signal output for character display comi1, comi2 o common signal output for horizontal icon display these are the same signal but the name is different. seg1 to seg128 o segment signal output for character display segi1 to segi4 o segment signal output for vertical icon display test pin table 3 . pin description (continued) name i/o description test1 to test 5 i test pin connect these to "low". note: dummy - these pins should be opened (floated).
65 com / 132 seg driver & controller for stn lcd ks 00 40 11 function description system interface KS0040 has two kinds interface type with mpu: bus mode (8- / 4-bit length), serial mode. serial and bus mode is selected by ps pin. table 4. various k inds of mpu i nterface ps mi if csb rs rw_wr e_rd db0 - 3 db4 - 5 db6 db7 8 bit (h) csb rs r/w e db0 - 3 db4 - 5 db6 db7 6800- series (h) 4 bit (l) csb rs (l) e * db4 - 5 db6 db7 8 bit (h) csb rs wr rd db0 - 3 db4 - 5 db6 db7 bus mode (h) 8080- series (l) 4 bit (l) csb rs wr (h)/(l) * db4 - 5 db6 db7 serial mode (l) (h)/(l) (h)/(l) csb rs (h)/(l) (h)/(l) * * scl si note: ?*? - don?t care ("high", "low" or "open") . (h)/(l): fixed ?high? (v dd ) or ?low? (v ss ) note: read operation is not permitted to 4-bit or serial interface mode. ps: "high" = p arallel interface mode, "low" = s erial interface mode mi: "high" = 6800- s eries mpu interface, "low" = 8080- s eries mpu interface mode if: "high" = 8- b it interface mode, "low" = 4- b it interface mode csb: "high" = c hip not selected, "low" = c hip selected rs: "high" = d ata register select, "low" = i nstruction r egister select rw_wr: 6800- s eries r ead / w rite select, 8080- s eries active "high " w rite enable e_rd: 6800- s eries "low" enable, 8080- s eries active "low " r ead enable scl (db6): s erial clock input si (db7): s erial data input
ks00 40 65 com / 132 seg driver & controller for stn lcd 12 interface with mpu in parallel bus mode (ps = "high") in parallel interface mode, 6800-series and 8080-series mpu is selected by mi pin, and interface bit length (8- / 4- bit) is selected by if pin. during write operation, the 16-bit data register (dr) and the 8-bit instruction register (ir) is used. the data register (dr) is used as temporary data storage place from mpu for being written into ddram / cgram / iconram. the target ram is selected by ram select ion instruction. the i nstruction register (ir) is used only to store instruction code transferred from mpu. to select either dr or ir, use the rs input pin in parallel mode or serial mode. csb if rs rw_wr e_rd db7 to db0 d3 to d0 xx d7 to d4 data write 4-bit bus mode (if = " low " ) 8-bit bus mode (if = " high " ) instruction write data read dummy read d7 to d0 d7 to d0 ~d0 d7 d3 to d0 d7 to d4 data write instruction write figure 3. timing d iagram of 6800-series b us m ode d ata t ransfer (mi = "high") csb if rs rw_wr e_rd db7 to db0 d3 to d0 xx d7 to d4 data write 4-bit bus mode (if = " low " ) 8-bit bus mode (if = " high " ) instruction write data read dummy read d7 to d0 d7 to d0 - d0 d7 d3 to d0 d7 to d4 data write instruction write figure 4. timing d iagram of 8080- s eries b us m ode d ata t ransfer (mi = "low")
65 com / 132 seg driver & controller for stn lcd ks00 40 13 interface with mpu in serial bus mode (ps = "low") when ps input pin is "low", clock synchronized serial interface mode is selected. at this time, the following four ports, scl (db6, synchronizing transfer clock input), si (db7, serial data input), and rs (register selection input), csb (chip selection input) are used. by setting csb to "low", KS0040 can receive scl input. if csb is set to "high", KS0040 initialize the interface circuit (8-bit shift register and 3-bit counter). serial data is input in the order of "d7, d6, d5, d4, d3, d2, d1, d0" from the serial data input pin (si = db7) at the rising edge of serial clock (scl = db6). at the rising edge of the 8th serial clock, the serial data (d7-d0) is converted into 8-bit bus data. the rs input of the dr / ir selection is latched at the rising edge of the 8th serial clock (scl). csb rs scl(db6) si(db7) d7 4 5 3 2 1 8 7 6 5 4 3 2 1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 figure 5. timing d iagram of s erial d ata t ransfer
ks00 40 65 com / 132 seg driver & controller for stn lcd 14 ram map internal ram has total 1,200 bytes, and consist of ddram (128 bytes), iconram (48 bytes) and cgram (1,024 bytes). table 5. ram map r3 r2 r1 r0 address ram data usage (d7~d0) ram size 0 0 0 0 00h - 0fh 10h - 1fh 20h - 2fh 30h - 3fh 40h - 4fh 50h - 5fh 60h - 6fh 70h - 7fh ddram (1 st line) ddram (2 nd line) ddram (3 rd line) ddram (4 th line) ddram (5 th line) ddram (6 th line) ddram (7 th line) ddram (8 th line) 128byte 0 0 0 1 00h - 0fh 10h - 1fh 20h - 2fh iconram upper 128 icons (c1 ~ c128) iconram lower 128 icons (c129 ~ c256) iconram coms data (s1 ~ s128) 48byte 1 0 0 0 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 1 st 16 x 16 pattern cgram 2 nd 16 x 16 pattern cgram 3 rd 16 x 16 pattern cgram 4 th 16 x 16 pattern 128byte (page 0) 1 0 0 1 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 5 th 16 x 16 pattern cgram 6 th 16 x 16 pattern cgram 7 th 16 x 16 pattern cgram 8 th 16 x 16 pattern 128byte (page 1) 1 0 1 0 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 9 th 16 x 16 pattern cgram 10 th 16 x 16 pattern cgram 11 th 16 x 16 pattern cgram 12 th 16 x 16 pattern 128byte (page 2) 1 0 1 1 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 13 th 16 x 16 pattern cgram 14 th 16 x 16 pattern cgram 15 th 16 x 16 pattern cgram 16 th 16 x 16 pattern 128byte (page 3) 1 1 0 0 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 17 th 16 x 16 pattern cgram 18 th 16 x 16 pattern cgram 19 th 16 x 16 pattern cgram 20 th 16 x 16 pattern 128byte (page 4) 1 1 0 1 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh c gram 21 st 16 x 16 pattern cgram 22 nd 16 x 16 pattern cgram 23 rd 16 x 16 pattern cgram 24 th 16 x 16 pattern 128byte (page 5) 1 1 1 0 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 25 th 16 x 16 pattern cgram 26 th 16 x 16 pattern cgram 27 th 16 x 16 pattern cgram 28 th 16 x 16 pattern 128byte (page 6) 1 1 1 1 00h - 1fh 20h - 3fh 40h - 5fh 60h - 7fh cgram 29 th 16 x 16 pattern cgram 30 th 16 x 16 pattern cgram 31 st 16 x 16 pattern cgram 32 nd 16 x 16 pattern 128byte (page 7) note : r3 - r 0 : ram / system select register ext = 1 ext = 0
65 com / 132 seg driver & controller for stn lcd ks00 40 15 display data ram (ddram) ddram stores 16-bits character code in fcgrom / cgram and 8-bits character code in hcgrom, and its maximum number is 128-byte (64-word: 64 characters of full-size fonts or 128 characters of half-size fonts). the displayable area is 64-byte and the other is extended data area. to display extended ddram data, set the ext bit "high" in system register set instruction. ddram address is set by the address counter (ac) as a hexadecimal number. msb lsb ac6 ac5 ac4 ac3 ac2 ac1 ac0 the relations of ddram address and display position when ddram is set to normal mode (ext = "low") 1st 2nd 3rd 4th 5th 6th 7th 8th com1 | com16 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f com17 | com32 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f com33 | com48 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f com49 | com64 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f (a) display shift is not performed 1st 2nd 3rd 4th 5 th 6th 7th 8th com1 | com16 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f com17 | com32 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f com33 | com48 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f com49 | com64 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f (b) display shift up is performed 1 st 2 nd 3 rd 4 th 5th 6th 7th 8th com1 | com16 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f com17 | com32 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f com33 | com48 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f com49 | com64 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f (c) display shift down is performed figure 6. normal mode ddram address (ext = " low " )
ks00 40 65 com / 132 seg driver & controller for stn lcd 16 when ddram is s et to extended mode (ext = "high") 1st 2nd 3rd 4th 5th 6th 7th 8th com1 | com16 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f com17 | com32 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f com33 | com48 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f com49 | com64 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f (a) display shift is not performed 1st 2nd 3rd 4th 5th 6th 7th 8th com1 | com16 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f com17 | com32 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f com33 | com48 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f com49 | com64 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f (b) display shift -u p is performed 1st 2nd 3rd 4 th 5th 6th 7th 8th com1 | com16 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f com17 | com32 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f com33 | com48 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f com49 | com64 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f (c) display shift -d own is performed figure 7. extended mode ddram address (ext = " high " )
65 com / 132 seg driver & controller for stn lcd ks00 40 17 character generator ram (cgram) cgram is used for user defined character pattern. it can generate 32,16 x 16 dots full-size fonts include cursor position. the capacity of cgram can support bitmap graphics 128 x 64 dot. to use the character pattern in cgram write the character code into ddram like t able 6. table 6 . relationship b etween character code (ddram) and character pattern (cgram) cgram address cgram data (a0 = 0) cgram data (a0 = 1) character code (ddram data) r r r r 3 2 1 0 a a a a a a 6 5 4 3 2 1 d d d d d d d d 7 6 5 4 3 2 1 0 d d d d d d d d 7 6 5 4 3 2 1 0 pattern n umber 0000h 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 pattern 1 : : : : : : 001fh 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 pattern 32
ks00 40 65 com / 132 seg driver & controller for stn lcd 18 table 7 . example for bitmap graphic by cgram cgram address cgram data (a0 = 0) cgram data (a0 = 1) pattern number character code (ddram data) r r r r 3 2 1 0 a a a a a a 6 5 4 3 2 1 d d d d d d d d 7 6 5 4 3 2 1 0 d d d d d d d d 7 6 5 4 3 2 1 0 0000h 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 pattern 1 0001h 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 pattern 2 : : : : : : character display cgram1 cgram3 cgram0 cgram2 fig ure 8 . example for bitmap display with character
65 com / 132 seg driver & controller for stn lcd ks00 40 19 (*16) (*15) | | | | | | | | | | (*6) (*5) (*4) (*3) (*2) (*1) (*1024) (*1023) | | | | | | | | | | (*1014) (*1013) (*1012) (*1011) (*1010) (*1009) fig ure 9 . relationship between cgram full graphic mode data writing and display pattern (fg = "high") during cgrom full graphic mode, cgram data is written from (*1) to (*1024) by 8-bit length table 8 . the order of cgram data writing (*1) (*2) (*3) (*4) (*5) (*6) --- --- --- --- (*15) (*16) (*17) (*18) (*19) (*20) *(21) (*22) --- --- --- --- (*31) (*32) | | | | | | | | | | | | | | | | | | | | | | | | (*1009) (*1010) (*1011) (*1012) (*1013) (*1014) --- --- --- (*1022) (*1023) (*1024)
ks00 40 65 com / 132 seg driver & controller for stn lcd 20 segment & common icon ram (iconram) iconram has segment / common icon pattern data. comi1 or comi2 and segi1~4 makes the data of iconram enable to display icons. table 9. relationship between iconram a ddress and d isplay p attern iconram address iconram bits a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 icons 0 0 0 0 vl1 vl2 vr1 vr2 vl3 vl4 vr3 vr4 0 0 0 1 vl5 vl6 vr5 vr6 vl7 vl8 vr7 vr8 : : 1 1 1 0 vl57 vl58 vr57 vr58 vl59 vl60 vr59 vr60 0 0 1 1 1 1 vl61 vl62 vr61 vr62 vl63 vl64 vr63 vr64 upper 128 segi icons data (*1) 0 0 0 0 vl65 vl66 vr65 vr66 vl67 vl68 vr67 vr68 0 0 0 1 vl69 vl70 vr69 vr70 vl71 vl72 vr71 vr72 : : 1 1 1 0 vl121 vl122 vr121 vr122 vl123 vl124 vr123 vr124 0 1 1 1 1 1 vl125 vl126 vr125 vr126 vl127 vl128 vr127 vr128 lower 128 segi icons data (*2) 0 0 0 0 h1 h2 h3 h4 h5 h6 h7 h8 0 0 0 1 h9 h10 h11 h12 h13 h14 h15 h16 : : 1 1 1 0 h113 h114 h115 h116 h117 h118 h119 h120 1 0 1 1 1 1 h121 h122 h123 h124 h125 h126 h127 h128 comi icons data (*3) note: v ln: vertical left n- th icon, vrn: vertical right n- th icon hn: horizontal n- th icon (where n = 1 to 128)
65 com / 132 seg driver & controller for stn lcd ks00 40 21 comi1 - h1 h2 h3 h4 --- h127 h128 com1 - vl1 vl2 vr1 vr2 com2 - vl3 vl4 vr3 vr4 com3 - | com31 - | | | | com32 - vl63 vl64 vr63 vr64 com33 - vl65 vl66 vr65 vr66 com34 - | com62 - | | | | com63 - vl125 vl126 vr125 vr126 com64 - vl127 vl128 character display area vr127 vr128 segi1- segi2- seg1- seg2- seg3- seg4- | seg127- seg128- segi3- segi4- (*3) (*1) (*2) figure 10. relationship between icon p attern d ata and com / seg l ine (when dirc = 0, dirs = 0) -segi4 -segi3 -seg128 -seg127 -seg126 -seg125 | -seg2 -seg1 -segi2 -segi1 com64 - vl1 vl2 vr1 vr2 com63 - vl3 vl4 vr3 vr4 com62 - | com34 - | | | | com33 - vl63 vl64 vr63 vr64 com32 - vl65 vl66 vr65 vr66 com31 - | com3 - | | | | com2 - vl125 vl126 vr125 vr126 com1 - vl127 vl128 character display area vr127 vr128 comi1 - h1 h2 h3 h4 -- h127 h128 (*3) (*1) (*2) figure 11. relationship between icon pattern data and com / seg line (when dirc = 1, dirs = 1)
ks00 40 65 com / 132 seg driver & controller for stn lcd 22 comi1 - h1 h2 h3 h4 -- h127 h128 com1 - vl1 vl2 vr1 vr2 com2 - vl3 vl4 vr3 vr4 com3 - | com31 - | | | | com32 - vl63 vl64 vr63 vr64 com33 - vl65 vl66 vr65 vr66 com34 - | com62 - | | | | com63 - vl125 vl126 vr125 vr126 com64 - vl127 vl128 character display area vr127 vr128 segi4- segi3- seg128- seg127- seg126- seg125- ~ seg2- seg1- segi2- segi1- (*3) (*1) (*2) figure 12. relationship between icon p attern d ata and com / seg l ine (when dirc = 0, dirs = 1) -segi1 -segi2 -seg1 -seg2 -seg3 -seg4 | -seg127 -seg128 -segi3 -segi4 com64 - vl1 vl2 vr1 vr2 com63 - vl3 vl4 vr3 vr4 com62 - | com34 - | | | | com33 - vl63 vl64 vr63 vr64 com32 - vl65 vl66 vr65 vr66 com31 - | com3 - | | | | com2 - vl125 vl126 vr125 vr126 com1 - vl127 vl128 character display area vr127 vr128 comi1 - h1 h2 h3 h4 -- h127 h128 (*3) (*1) (*2) figure 13. relationship between icon p attern d ata and com / seg l ine (when dirc = 1, dirs = 0)
65 com / 132 seg driver & controller for stn lcd ks 00 40 23 character generator rom for a full-size font (fcgrom) fcgrom generates 16 x 16 characters pattern from character generate code in ddram. fcgrom has 16 x 16-dot 8,160 character pattern include cursor position for asian language character font (like chinese, japanese kanji, korean). if the data in cursor position bit are high, the data are included to the character pattern. so, the selected positions are always on without regard to cursor position. character generator rom for a half-size font (hcgrom) hcgrom generates 8 x 16 characters pattern from character generate code in ddram. hcgrom has 8 x 16- dot 128 character pattern include cursor position for half-size font (like alphanumeric characters and symbols). if the data in cursor position bit are high, the data are included to the character pattern. so, the selected positions are always on without regard to cursor position. table 10. relationship between cgrom a ddress and font p attern (KS0040-00 font) fcgrom address font data (d15 ~ d0) h cgrom address font data (d 7 ~ d0) a13 ~ a0 f e f c b a 9 8 7 6 5 4 3 2 1 0 a 6 ~ a0 7 6 5 4 3 2 1 0 03 80(h) 41 (h)
ks00 40 65 com / 132 seg driver & controller for stn lcd 24 table 11. KS0040 - 00 font ( ksc5601 c ode) map ksc5601 code KS0040 fcgrom code font data - 0000 (h) ~ 001f (h) cgram font area a1a1 (h) ~ acfe (h) 0020 (h) ~ 037f (h) symbol character area b0a1 (h) ~ b0fe (h) b1a1 (h) ~ b1fe (h) b2a1 (h) ~ b2fe (h) b3a1 (h) ~ b3fe (h) b4a1 (h) ~ b4fe (h) b5a1 (h) ~ b5fe (h) b6a1 (h) ~ b6fe (h) b7a1 (h) ~ b7fe (h) b8a1 (h) ~ b8fe (h) b9a1 (h) ~ b9fe (h) baa1 (h) ~ bafe (h) bba1 (h) ~ bbfe (h) bca1 (h) ~ bcfe (h) bda1 (h) ~ bdfe (h) bea1 (h) ~ befe (h) bfa1 (h) ~ bffe (h) c0a1 (h) ~ c0fe (h) c1a1 (h) ~ c1fe (h) c2a1 (h) ~ c2fe (h) c3a1 (h) ~ c3fe (h) c4a1 (h) ~ c4fe (h) c5a1 (h) ~ c5fe (h) c6a1 (h) ~ c6fe (h) c7a1 (h) ~ c7fe (h) c8a1 (h) ~ c8fe (h) 0380 (h) ~ 03dd (h) 03de (h) ~ 043b (h) 043c (h) ~ 0499 (h) 049a (h) ~ 04f7 (h) 04f8 (h) ~ 0555 (h) 0556 (h) ~ 05b3 (h) 05b4 (h) ~ 0611 (h) 0612 (h) ~ 066f (h) 0670 (h) ~ 06cd (h) 06ce (h) ~ 072b (h) 072c (h) ~ 0789 (h) 078a (h) ~ 07e7 (h) 07e8 (h) ~ 0845 (h) 0846 (h) ~ 08a3 (h) 08a4 (h) ~ 0901 (h) 0902 (h) ~ 095f (h) 0960 (h) ~ 09bd (h) 09bc (h) ~ 0a1b (h) 0a1c (h) ~ 0a7c (h) 0a7d (h) ~ 0ad7 (h) 0ad8 (h) ~ 0b35 (h) 0b36 (h) ~ 0b93 (h) 0b94 (h) ~ 0bf1 (h) 0bf2 (h) ~ 0c4f (h) 0c50 (h) ~ 0cad (h) caa1 (h) ~ caf (h) cba1 (h) ~ cbfe (h) cca1 (h) ~ ccfe (h) cda1 (h) ~ cdfe (h) cea1 (h) ~ cefe (h) cfa1 (h) ~ cffe (h) d0a1 (h) ~ d0fe (h) d1a1 (h) ~ d1fe (h) d2a1 (h) ~ d2fe (h) d3a1 (h) ~ d3fe (h) d4a1 (h) ~ d4fe (h) d5a1 (h) ~ d5fe (h) d6a1 (h) ~ d6fe (h) d7a1 (h) ~ d7fe (h) d8a1 (h) ~ d8fe (h) d9a1 (h) ~ d9fe (h) daa1 (h) ~ dafe (h) dba1 (h) ~ dbfe (h) dca1 (h) ~ dcfe (h) dda1 (h) ~ ddfe (h) 0cb0 (h) ~ 0d0d (h) 0d0e (h) ~ 0d6b (h) 0d6c (h) ~ 0dc9 (h) 0dca (h) ~ 0e27 (h) 0e28 (h) ~ 0e85 (h) 0e86 (h) ~ 0ee3 (h) 0ee4 (h) ~ 0f41 (h) 0f42 (h) ~ 0f9f (h) 0fa0 (h) ~ 0ffd (h) 0ffe (h) ~ 105b (h) 105c (h) ~ 10b9 (h) 10ba (h) ~ 1117 (h) 1118 (h) ~ 1175 (h) 1176 (h) ~ 11d3 (h) 11d4 (h) ~ 1231 (h) 1232 (h) ~ 128f (h) 1290 (h) ~ 12fd (h) 12ee (h) ~ 134b (h) 134c (h) ~ 13a9 (h) 13aa (h) ~ 1407 (h)
65 com / 132 seg driver & controller for stn lcd ks00 40 25 table 11. KS0040f00 font ( ksc5601 c ode) map (continued) ksc5601 code KS0040 fcgrom code font data dea1 (h) ~ defe (h) dfa1 (h) ~ dffe (h) e0a1 (h) ~ e0fe (h) e1a1 (h) ~ e1fe (h) e2a1 (h) ~ e2fe (h) e3a1 (h) ~ e3fe (h) e4a1 (h) ~ e4fe (h) e5a1 (h) ~ e5fe (h) e6a1 (h) ~ e6fe (h) e7a1 (h) ~ e7fe (h) e8a1 (h) ~ e8fe (h) e9a1 (h) ~ e9fe (h) eaa1 (h) ~ eafe (h) eba1 (h) ~ ebfe (h) eca1 (h) ~ ecfe (h) eda1 (h) ~ edfe (h) eea1 (h) ~ eefe (h) eea1 (h) ~ effe (h) f0a1 (h) ~ f0fe (h) f1a1 (h) ~ f1fe (h) f2a1 (h) ~ f2fe (h) f3a1 (h) ~ f3fe (h) f4a1 (h) ~ f4fe (h) f5a1 (h) ~ f5fe (h) f6a1 (h) ~ f6fe (h) f7a1 (h) ~ f7fe (h) f8a1 (h) ~ f8fe (h) f9a1 (h) ~ f9fe (h) faa1 (h) ~ fafe (h) fba1 (h) ~ fbfe (h) fca1 (h) ~ fcfe (h) fda1 (h) ~ fdfe (h) 1408 (h) ~ 1465 (h) 1466 (h) ~ 14c3 (h) 14c4 (h) ~ 1521 (h) 1522 (h) ~ 157f (h) 1580 (h) ~ 15dd (h) 15de (h) ~ 163b (h) 163c (h) ~ 1699 (h) 169a (h) ~ 16f7 (h) 16f8 (h) ~ 1755 (h) 1756 (h) ~ 17b3 (h) 17b4 (h) ~ 1811 (h) 1812 (h) ~ 186f (h) 1870 (h) ~ 18cd (h) 18ce (h) ~ 192b (h) 192c (h) ~ 1989 (h) 198a (h) ~ 19e7 (h) 19e8 (h) ~ 1a45 (h) 1a46 (h) ~ 1aa3 (h) 1aa4 (h) ~ 1b01 (h) 1b02 (h) ~ 1b5f (h) 1b60 (h) ~ 1bbd (h) 1bbe (h) ~ 1c1b (h) 1c1c (h) ~ 1c79 (h) 1c7a (h) ~ 1cd7 (h) 1cd8 (h) ~ 1d35 (h) 1d36 (h) ~ 1d93 (h) 1d94 (h) ~ 1df1 (h) 1df2 (h) ~ 1e4f (h) 1e50 (h) ~ 1ead (h) 1eae (h) ~ 1f0b (h) 1f0c (h) ~ 1f69 (h) 1f6a (h) ~ 1fc7 (h)
ks00 40 65 com / 132 seg driver & controller for stn lcd 26 low power consumption mode KS0040 has sleep mode for saving power consumption during standby period. ( refer to "initializing & power save mode setup") sleep mode in the sleep mode, the power circuit and the oscillation circuit are turned off . this mode helps to save power consumption by reducing current to almost resting current level. 1. liquid c rystal d isplay o utput com1 to com64, comi1, 2: v ss level seg1 to seg128, segi1, 2, 3, 4: v ss level 2. ddram, cgram, iconram and register written information are saved. 3. operation mode is retained the same as it was prior to execution of the sleep mode. all internal circuits are stopped. 4. power c ircuit and o scillation c ircuit the built-in supply circuit and the oscillation circuit are turned off automatically by using the sleep command. lcd driving circuit lcd driver circuit has 65 common and 132 segment signals for lcd driving. the data from c grom / cgram / iconram is transferred to 128-bit segment latch serially by 8-bits unit, and then it is stored to 128-bit shift latch. the data from iconram is stored to 4-bit latch. when each common line is selected by 65-bit common register, segment data and segment icon data also output through segment driver from 128-bit segment latch and 4-bit segment icon latch. KS0040 has common and segment bi-directional function to help various panel application s . ( refer to t able 12 and t able 13 ) table 12. seg data shift direction dirs seg data shift direction low segi1, segi2, seg1 ? - - - - - - - ? seg128, segi3, segi4 high segi4, segi3, seg128 ? - - - - - - - ? seg1, segi2, segi1 table 13. com data shift direction duty dirc com data shift direction low com1 ? - - - - - - - ? com16, comi1 (comi2) 1/17 (1-line mode) high com16 ? - - - - - - - ? com1, comi1 (comi2) low com1 ? - - - - - - - ? com32, comi1 (comi2) 1/33 (2-line mode) high com32 ? - - - - - - - ? com1, comi1 (comi2) low com1 ? - - - - - - - ? com48, comi1 (comi2) 1/49 (3-line mode) high com48 ? - - - - - - - ? com1, comi1 (comi2) low com1 ? - - - - - - - ? com64, comi1 (comi2) 1/65 (4-line mode) high com64 ? - - - - - - - ? com1, comi1 (comi2)
65 com / 132 seg driver & controller for stn lcd ks00 40 27 display shift control KS0040 has v ertical dot-by-dot or character-by-character shift function, which are usable when display panel size is less than 4-line display and want to display the hidden-line data, or when extended ddram is set and want to display extended ddram data after 1st dot-by-dot shift -u p display home state after 2nd d o t-by-dot shift -u p after 4th d o t-by-dot shift -u p after 16th d o t-by-dot shift -u p figure 14. vertical dot-by-dot shift -u p ( d own) example
ks00 40 65 com / 132 seg driver & controller for stn lcd 28 instruction description outline to overcome the speed difference between internal clock of KS0040 and mpu clock, KS0040 performs internal operation by storing control information to ir or dr. the internal operation is determined according to the signal from mpu, composed of read / write and data bus. instruction can be divided four kinds, (1) system register set instructions (power control, contrast value set, etc.) (2) internal ram access instructions (ram select, ram address set, data read / write, etc.) (3) display control instructions (vertical shift, double height character , etc.) (4) o thers the address of internal ram is automatically increased or decreased by 1. note : every instruction takes one cycle execution time, so to execute the next instruction, minimum e cycle time ( tc) must be kept.
65 com / 132 seg driver & controller for stn lcd ks00 40 29 table 14. instruction table instruction code instruction rs db7 db6 db5 db4 db3 db2 db1 db0 description nop 0 0 (hex) 0 0 0 0 no operation return home 0 1 (hex) - - - - set ddram address to "00h" from ac and return cursor to its original position if shifted. the contents of ddram are not changed display control 0 2 (hex) d cc lc rev display (d), c haracter c ursor (cc), l ine c ursor (lc), b/w r everse d isplay (rev) on / off control power save mode 0 3 (hex) - - - slp sleep mode (slp) on / off control contrast increment / decrement 0 4 (hex) - - - cid contrast i ncrement (cid = 1) or d ecrement (cid = 0) vertical shift 0 5 (hex) - - cd ud vertical c haracter (cd = 1), d ot (cd = 0) s hift -u p (ud = 1), d own (ud = 0) double height character 0 6 (hex) - en dh1 dh0 double height character enable (en) at selected line (dh1 , dh0). r3 r2 r1 r0 selected ram / register 0 0 0 0 0 0 0 1 1 0 0 0 - 1 1 1 1 ddram iconram cgram page 0 - cgram page 7 ram select / system register set 0 7 (hex) r3 r2 r1 r0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 power control register contrast control register environment control register function control register ram address set 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 dd / cg / icon ram address setting, one of 3 ram is selected by ram select instruction. write data 1 d7 d6 d5 d4 d3 d2 d1 d0 dd / cg / icon ram and system register data write read data 1 d7 d6 d5 d4 d3 d2 d1 d0 dd / cg / icon ram and system register data read note: " - " - don?t care
ks00 40 65 com / 132 seg driver & controller for stn lcd 30 table 15. system register values register select bit register value map r3 r2 r1 r0 selected system register db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 *1) power control register osc vc vr vf intr rr2 rr1 rr0 0 1 0 1 *2) contrast control register - - c5 c4 c3 c2 c1 c0 0 1 1 0 *3) environment control register - - dt1 dt0 dirc dirs ext id 0 1 1 1 *4) function control register - - - fg cm fl1 b1 b0 n ote : " - " - don?t care *1) osc : i nternal o scillator on (osc = 1), off (osc = 0) control bit vc : v oltage c onverter on (vc = 1), off (vf = 1) control bit vr : v oltage r egulator on (vr = 1), off (vr = 0) control bit vf : v oltage f ollower on (vf = 1), off (vf = 0) control bit intr : u se the internal voltage regulating resisters on (intr = 1), off (intr = 0) control bit rr2 to rr0 : i nternal voltage adjusting resisters set control register bits (refer to table 18 ) *2) c5 to c0 : el ectronic contrast control register bits. ( refer to figure 21 ) *3) dt1, dt0 : d uty select bits (refer to table 15 ) dirc, dirs : c ommon data direction (dirc), segment data direction (dirs) select bit (refer to table 12 and table 13 ) ext : ddram extended mode on (ext = 1), off (ext = 0) control bit id : ddram / cgram / iconram address increment (id = 1), decrement (id = 0) control bit *4) fg : c gram full graphic mode on (fg = 1), off (fg = 0) control bit cm : c enter display mode on (cm = 1), off (cm = 0) control bit fl1 : f irst line fix mode on (fl1 = 1), off (fl1 = 0) control, during vertical shift b1, b0 : c ursor attribute control bit
65 com / 132 seg driver & controller for stn lcd ks00 40 31 return home rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 - - - - set ddram address to "00h" into the address counter. if the display position has shifted, it return to the original positions. when cursor or blinking is displayed on, bring the cursor to the left edge on first line of the display. the data in ddram does not change. display control rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 d cc lc rev display control bit on / off instruction d: display on / off contro l when d = "high", entire display is turned on when d = "low", entire display is turned off, but display data is remained in ddram (default) cc: character cursor on / off control bit when cc = "high", character cursor is turned on. when cc = " low", character cursor is disappeared in current display (default) . lc: line cursor on / off control bit when lc = "high", line cursor is turned on according to the most significant 2-bits ( addr[6], addr[5]) of current ddram address (addr [6:0]) . when lc = " l ow", line cursor is disappeared in current display (default) rev: black / white reverse display on / off control bit when rev= "high", all the display area except icon area are black / white reversed . when rev= " low", normal display status (default) power save mode rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 - - - slp power save mode is used to making KS0040 sleep mode. slp: sleep mode on / off control bit when slp = "high", sleep mode is set (default). when slp = "low", sleep mode is reset. ( refer to "l ow p ower c onsumption m ode " and "i nitializing & p ower s ave m ode s etup ")
ks00 40 65 com / 132 seg driver & controller for stn lcd 32 contrast increment / decrement rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 - - - cid contrast control register value increment / decrement instruction cid: contrast increment / decrement enable bit when cid = ?high?: c ontrast register value increased by 1 until 63 . when cid = ?low?: c ontrast register value decreased by 1 until 0 . vertical shift -u p / d own rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 - - cd ud vertical dot-by-dot display shift - up / down instruction (refer to figure 14, 16 ) cd: character / dot shift select bit when cd = "high" : d isplay shift - up / down by character is selected (it?s the same as 16-time dot shift) . when cd = "low": d isplay shift - up / down by dot is selected . ud: vertical display shift direction select when ud = "high" : d isplay shift - up is performed . when ud = "low" : d isplay shift - down is performed . double height character rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 - en dh1 dh0 double height character instruction (refer to figure 15 ) en: double height character mode enable bit when en = "high": d ouble height character mode is enabled . when en = "low": d ouble height character mode is disabled (default) . dh1, dh0: double height character line select when [dh1, dh0] = [low, low]: 1, 2 - line becomes double height character = [low, high]: 2, 3 - line becomes double height character = [high, low]: 3, 4 - line becomes double height character = [high, high]: 1 to 4 - line becomes double height character
65 com / 132 seg driver & controller for stn lcd ks00 40 33 ram select / system register set rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 r3 r2 r1 r0 ram select ion (ddram / cgram / iconram) or system register set instruction. r3 / r2 / r1 / r0: ram or s ystem register select ion bits select bits data length / value map r3 r2 r1 r0 selected ram or registers db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 ddram iconram cgram page0 cgram page1 cgram page2 cgram page3 cgram page4 cgram page5 cgram page6 cgram page7 1-byte (half-size font) 2-byte (full-size font) 1-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 power control register contrast control register environment control register function control register osc - - - vc - - - vr c5 dt1 - vf c4 dt0 fg intr c3 dirc cm rr2 c2 dirs fl1 rr1 c1 ext b1 rr0 c0 id b0 n ote : " - " - don?t care for writing 2-byte data into ram, data write instruction must be performed twice. osc: oscillator circuit on (osc = "high"), off (osc = "low": default) control vc / vr / vf: voltage converter / regulator / follower circuit on (vc / vr / vf = "high"), off (vc / vr / vf = "low": default) control i ntr: use the internal voltage regulating resistors on (intr = "high"), off (intr = "low": default) control bit rr2~rr0: internal voltage adjusting resistors set control register bits ([0,0,0]: default). ( refer to table 18 ) c5 to c0: electronic contrast control register ([0, 0, 0, 0, 0, 0]: default) (refer to figure 21 ) dt1, dt0: duty select register ([1, 1]: default) (refer to table 18 ) dirc, dirs: common data shift direction (dirc), segment data shift direction (dirs) flag register ([0, 0]: default) (refer to table 12 and table 13 ) ext: ddram extended mode on (ext = "high"), off (ext = "low": default) control id: ram address increment (id = "high": default), decrement (id = "low") mode set fg: cgram full graphic mode on / off control register (fg = "low": default). ( refer to figure 18 ) cm: center display mode on / off control register (cm = "low": default). ( refer to figure 17 ) fl1: first line fix mode, during vertical scroll instruction, on / off control register (fl1 = "low": default). ( refer to figure 16 ) b1, b0: character / line cursor attribute select register ([0, 0]: default) (refer to table 17 )
ks00 40 65 com / 132 seg driver & controller for stn lcd 34 ram address set rs db7 db6 db5 db4 db3 db2 db1 db0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 ddram / cgram / iconram address set instruction . each ram is selected by ram select instruction . write data rs db7 db6 db5 db4 db3 db2 db1 db0 1 d7 d6 d5 d4 d3 d2 d1 d0 ddram / cgram / iconram data or s ystem r egister value write instruction . each ram and s ystem r egister is selected by ram select / system register set instruction. after write operation, the address is increased/decreased by 1 automatically, according to function control register set. when writing full-size character address in fcgrom to ddram, ram data write instruction must be written twice , because the fcgrom address is 13-bits long. ( refer to figure 15 ) read data (8-bit b us m ode mpu i nterface only) rs db7 db6 db5 db4 db3 db2 db1 db0 1 d7 d6 d5 d4 d3 d2 d1 d0 ddram / cgram / iconram data or system register value read instruction . each ram and system register is selected by ram select / system register set instruction. if you read ram data after ram address set instruction, you can get correct ram data from the second. the first data would be incorrect, because there is no timing margin for transfer ram data to output register. after write or read operation, the address is increased/decreased by 1 automatically, according to function control register set. when reading full size character address in fcgrom from ddram, ram data read instruction must be executed twice , because the fcgrom address is 13-bits long. ( refer to figure 15 )
65 com / 132 seg driver & controller for stn lcd ks00 40 35 full-size character code (fcgrom / cgram address + attribute) 0 [ a1] [ a 0 ] c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 half-size character code (hcgrom address) 1 c6 c5 c4 c3 c2 c1 c0 upper character code display a ttribute c ode full-size character lower character code character code half-size character figure 15. ddram data (fcgrom / hcgrom / cgram address) format table 16. display attributes [a1] [a0] display state ( w hen cursor / blink off) 0 0 normal display 0 1 b/w reversed display 1 0 character blink mode 1 1 1 character blink mode 2
ks00 40 65 com / 132 seg driver & controller for stn lcd 36 table 17 cursor attributes [b1] [b0] display state (at cursor position) 0 0 underline cursor 0 1 b/w reverse cursor 1 0 blink cursor 1 1 1 blink cursor 2 table 18. the r elationship between d uty and e nvironment s et dt1 dt0 duty bias fosc (khz) display line number 0 0 1/17 1/5 24.5 1-line display 0 1 1/33 1/7 47.6 2-line display 1 0 1/49 1/8 68.3 3-line display 1 1 1/65 1/9 93.7 4-line display
65 com / 132 seg driver & controller for stn lcd ks00 40 37 normal display l line cursor (lc) off l first line fix mode (fl1) off l vertical shift off normal display & line cursor l line cursor (lc) on (b1, b0 = [0, 1]) l first line fix mode (fl1) off l vertical shift off vertical shifted display (in first line fix mode) line cursor (lc) on (b1, b0 = [0, 1]) l first line fix mode (fl1) on l vertical shift -u p by dot 6 times vertical shifted display ( in first line fix mode ) l line cursor (lc) on (b1,b0 = [0, 1]) l first line fix mode (fl1) on l vertical shift up by dot 16 times or vertical shift -u p by character o nce figure 16. the examples of vertical shift and first line fix mode
ks00 40 65 com / 132 seg driver & controller for stn lcd 38 (a) dh1, dh0 = [0, 0 ] (b) dh1, dh0 = [0, 1] (c) dh1, dh0 = [ 1 , 0 ] (d) dh1, dh0 = [ 1 , 1] (e) dh1, dh0 = [0, 0 ] and center mode on (cm = 1), when 3-line display figure 17 . the examples of double height character display
65 com / 132 seg driver & controller for stn lcd ks00 40 39 figure 18 . the examples of full graphic mode display (fg = 1)
ks00 40 65 com / 132 seg driver & controller for stn lcd 40 initializing & power save mode setup hardware reset when reset pin = "active (rising or falling)", KS0040 can be initialized the following state. return home address counter = 00h control display on / off instruction d = 0: display off cc, lc = [0, 0]: character / l ine cursor off rev = 0: reverse display off (normal display) power save mode instruction slp = 1: s leep mode on ram select instruction r3 to r0 = [0, 0, 0, 0]: ddram is selected . system register set instruction osc = 0: oscillator off vc, vr, vf = [0, 0, 0]: voltage converter / regulator / follower off intr = 0: internal voltage regulating resister off rr2 to rr0 = [0, 0, 0]: i nternal voltage adjusting resistors set control register value are set to 000 . c5 to c0 = [0, 0, 0, 0, 0, 0]: e lectronic contrast control register value s are set to 00h . dt1, dt0 = [1, 1]: 4-line display mode dirc = 0: normal direction of common outputs (com1 to com64, comi1 (comi2)) dirs = 0: normal direction of segment outputs (segi1, segi2, seg1 to seg128, segi3, segi4) ext = 0: n ormal ddram mode is selected . id = 1: ram address increment condition fg = 0: cgram full graphic mode off cm = 0: center display mode off fl1 = 0: first line fix mode off b1, b0 = [0, 0]: u nder line cursor attribute is selected. note : if initialization is not done by reset pin, unstable condition might result. s o, for initializing the reset input pin must be active at first.
65 com / 132 seg driver & controller for stn lcd ks00 40 41 reset s tart t ime t resetb 50 ns reset p ulse w idth t rw 1.0 m s reset t ime t r 1.0 m s t r t rw v dd =2.4v t resetb v dd reset internal reset time figure 19 . reset timing note : t rw indicates the minimum reset duration for activat ing internal reset signal. t r indicates reset completion time of internal circuit from the edge of the internal reset signal.
ks00 40 65 com / 132 seg driver & controller for stn lcd 42 initializing by instruction note : commands (3) and (4) initialize the ram. the non-display area must satisfy the following conditions (for ram clear). ddram: write the a0h data. (half character flag "1" and space character code "20h": "1" "0100000") cgram: write the 00h data (blank data) iconram: write the 00h data (off data) as the ram data is unstable during reset signal input (after power on), blank data must be written. if not, unexpected display may result. input of ram (data) write command input of ram address setup command display of written data end of initialization command input (5) display control commands d: on command input (1) power save set command slp = off (sleep mode off) (2) system register set command a. environment register value set (dt1, dt0, dirc, dirs, ext, id) b. function control register value set (fg, cm, fl1, b1, b0) c. internal voltage adjusting resistors set control register set (rr2~rr0) d. contrast control register value set (c5 to c0) e. power control register value set (osc ? vc ? vr (intr) ? vf: on) (3) ram address set command (4) data writing (ram clear) (ddram = a0h, cg/ iconram = 00h) waiting for 10 m sec or more input of reset signal power regulation v dd -v ss power on command status initializing by hardware reset input status waiting for 20msec or more
65 com / 132 seg driver & controller for stn lcd ks00 40 43 sleep mode set or release by instruction sleep mode setting sleep mode releasing internal voltage regulating resistor control bit (intr) and voltage adjusting resistors set control register bits (rr2 - rr0) are not changed in sleep mode. enter the sleep mode command input (1) display on / off control command d = off (display off) (2) power save set command slp = on (power save on) *osc, vc, vr, vf are automatically off . command status initializing by instruction setup input status normal operation status end of initialization return to normal operation waiting for 20 ms or more command input (1) power save set command slp = off (sleep mode off) (2) system register set command (power control register set) * osc ? vc ? vr ? vf : on (3) display control command d = on (display on ) end of initialization
ks00 40 65 com / 132 seg driver & controller for stn lcd 44 recommendation of power on / off sequence power on sequence (power control register set) power off sequence oscillator on [osc, vc, vr, vf = 1, 0, 0, 0] v dd - v ss power on voltage converter on [osc, vc, vr, vf = 1, 1, 0, 0] voltage regulator on [osc, vc, vr, vf = 1, 1, 1, 0] voltage follower on [osc, vc, vr, vf = 1, 1, 1, 1] waiting for 3 1ms waiting for 3 1ms waiting for 3 1ms display off voltage regulator off [osc, vc, vr, vf = 1, 1, 0, 1] voltage follower off [osc, vc, vr, vf = 1, 1, 0, 0] voltage converter off [osc, vc, vr, vf = 1, 0, 0, 0] waiting for 3 50 ms waiting for 3 1ms waiting for 3 1ms waiting for 3 1ms v dd -v ss power off
65 com / 132 seg driver & controller for stn lcd ks00 40 45 lcd driving power supply circuit this power supply circuit generating voltages to drive lcd consists of voltage converter, voltage regulator, and voltage follower. voltage converter boosts up logic voltage (v dd ) 2, 3 and 4 times and this boosted voltage (v out ) is delivered to the voltage regulator. voltage regulator adjusts v0 between v out and v ss and this adjusted voltage is sent to the voltage follower. v lcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4) and those output impedance are converted by the voltage follower for increasing drive capability. power supply circuit is controlled by the power control instruction. there can be eight combination states according to instruction sets (vc, vr and vf). table 19 shows useful combinations which are recommended, and the remaining combination states are impractical, not recommended to be used. table 19. recommended p ower s upply c ombination vc vr vf voltage converter voltage regulator voltage follower vout vo,vr v1, v2, v3, v4 1 1 1 enable enable enable internal voltage output used for voltage adjustment internal voltage output 0 1 1 disable enable enable external voltage input used for voltage adjustment internal voltage output 0 0 1 disable disable enable open vo: external voltage input vr: open internal voltage output 0 0 0 disable disable disable open vo: external voltage input vr: open external voltage input note : sec recommendation is to use only the case listed above table.
ks00 40 65 com / 132 seg driver & controller for stn lcd 46 voltage converter this circuit boosts up the electric potential between v dd and v ss to 2, 3 or 4 times toward positive side and boosted voltage come out through v out terminal. * recommended capacitance value is 1 m f v dd v out cap3+ cap3- cap2+ cap2- cap1+ cap1- v ss gnd v dd v ss c1 c1 v dd v out = 2 x v dd figure 20. two t imes b oosting * recommended capacitance value is 1 m f gnd v dd v ss c1 c1 v dd v out = 3 x v dd c1 gnd v dd v ss c1 c1 v dd v dd v out cap3+ cap3- cap2+ cap2- cap1+ cap1- v ss figure 21. three t imes b oosting
65 com / 132 seg driver & controller for stn lcd ks00 40 47 * recommended capacitance value is 1 m f v dd v out cap3+ cap3- cap2+ cap2- cap1+ cap1- v ss gnd v dd v ss c1 c1 v dd v out = 4 x v dd c1 c1 figure 22. four t imes boost ing
ks00 40 65 com / 132 seg driver & controller for stn lcd 48 voltage regulator the boosting voltage occurring at v out is sent to the voltage regulator. the voltage regulator determines v0 lcd driver voltage by adjusting resistor ra and rb within the range of |v0| < |v out |. this v0 is determined by equation (1) , where ra and rb are internal or external resistors and v ref is determined by equation (2) as the voltage source of the ic. the electric potential of v ref is set to one of 64 levels by setting 6-bit reference voltage register. rb v0 = (1 + ?? ) x v ev [ v ] ------ (1) ra (63 - a ) v ev = (1 - ????? ) x vs [ v ] ------- (2) 300 where a = value of 6-bit reference voltage register (0 to 63) when ref = "high", vs = v dd ref = "low", vs = v ref (internal reference voltage) = 2v v s inside chip gnd v ss vout v dd v ref ref rb ra v0 vr - + + - v ev figure 23. voltage r egulator c ircuit
65 com / 132 seg driver & controller for stn lcd ks00 40 49 when using internal resistors, ra and rb (intr = "high") when intr bit is set to " high ", resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 20 . internal rb / ra ratio depending on 3-bit data (r r 2 r r 1 r r 0) 3-bit d ata settings (r r 2 r r1 r r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1+(rb / ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 the following figure shows v0 voltage measured by adjusting internal regulator re s ist o r ratio ( rb / ra) and 6-bit electronic volume registers at ta = 25 c ( temperature coefficient = -0.05%/ c ) . 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 electronic volume level v0 [v] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) figure 24 . electronic v olume l evel (temperature coefficient = -0.05% / c)
ks00 40 65 com / 132 seg driver & controller for stn lcd 50 table 21. the r elationship between e lectronic v olume c onstant, a a , and 6-bit v oltage refer ence r egister (c5, c4, c3, c2, c1, c0) c5 c4 c3 c2 c1 c0 a a 1 1 1 1 1 1 63 1 1 1 1 1 0 62 . . . . . . . . . . . . . . 0 0 0 0 0 1 1 0 0 0 0 0 0 0 table 22. the c hange r atio of v ref and v0 by a a is as f ollowing t able ( ref = l, [ rr2, rr1, rr0 ] = [ 1, 0, 0 ], ta = 25 c ) a a 0 1 - - - 30 31 32 - - - 62 63 v0 7.90 7.93 - 8.90 8.93 8.97 - 9.97 10.00
65 com / 132 seg driver & controller for stn lcd ks 00 40 51 when using external resistors, ra and rb (intr = "low") when intr bit is set to "low", it is necessary to connect external regulator resistor ra between vr and v ss , and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1, 1, 1, 1, 1, 1) 3. m aximum current flowing ra, rb = 1 m a from equation (1) rb v0 = 10 [v] = (1 + ?? ) x v ref ------ ( 2 ) ra from equation (2) 0 v ref = (1 - ??? ) x vs = vs = 2v or v dd ------ ( 3 ) 300 where a = 63 vs = 2v or v dd from requirement 3. 10 ???? = 1 [ m a ] ------ ( 4 ) ra + rb from equations ( 2 ) , ( 3 ) and ( 4 ) a. when vs = 2v (ref = "low") ra = 2 [m w ] rb = 8 [m w ] b. when vs = v dd = 3v (ref = "high") ra = 3 [m w ] rb = 7 [m w ]
ks00 40 65 com / 132 seg driver & controller for stn lcd 52 lcd bias resistor & follower v dd cap1+ cap1- cap2+ cap2- cap3+ cap3- vout vr v0 v1 v2 v3 v4 v ss gnd v dd c1 a) when use the internal bias circuit (vc, vr, vf, intr = [ 1, 1, 1, 1 ] ) * recommended capacitance value is 1 m f b) when use the external bias circuit (vc, vr, vf, intr = [ 1, 1, 0, 1 ] ) c1 c1 c1 c1 c1 c1 c1 c1 v dd cap1+ cap1- cap2+ cap2- cap3+ cap3- vout vr v0 v1 v2 v3 v4 v ss gnd v dd c1 c1 c1 c1 c1 r1 c1 c1 c1 c1 r1 r2 r1 r1 figure 25. lcd bias circuit table 23. duty select input & internal bias circuit dt1 dt0 duty internal bias low low 1/17 1/5 low high 1/33 1/7 high low 1/49 1/8 high high 1/65 1/9
65 com / 132 seg driver & controller for stn lcd ks00 40 53 use the external power supply v dd cap1+ cap1- cap2+ cap2- cap3+ cap3- vout vr v0 v1 v2 v3 v4 v ss gnd v dd (vc, vr, vf, intr = [ 0, 1, 1, 1 ] ) (vc, vr, vf, intr = [ 0, 1, 1, 0 ] ) c1 c1 c1 c1 c1 v dd cap1+ cap1- cap2+ cap2- cap3+ cap3- vout vr v0 v1 v2 v3 v4 v ss gnd c1 c1 c1 c1 external power supply ra c1 rb v dd external power supply v dd cap1+ cap1- cap2+ cap2- cap3+ cap3- vout vr v0 v1 v2 v3 v4 v ss gnd c1 c1 c1 c1 v dd external power supply v dd cap1+ cap1- cap2+ cap2- cap3+ cap3- vout vr v0 v1 v2 v3 v4 v ss gnd v dd external power supply * recommended capacitance value is 1 m f (vc, vr, vf, intr = [ 0, 0, 0, 0 ] ) (vc, vr, vf, intr = [ 0, 0, 1, 0 ] ) figure 26. when e xternal power supply is used
ks00 40 65 com / 132 seg driver & controller for stn lcd 54 application information mpu interface method parallel i nterfacing with 8080-series m icroprocessors vdd rs ps csb mi KS0040 e_rd rw_wr d b 0 - d b 7 reset vss vcc a0 a1~a7 iorq mpu (8080-series) rd wr d0 - d7 reset gnd decoder gnd vcc resetb vcc gnd figure 27. 8080-series mpu interface parallel i nterfacing with 6800-series m icroprocessors vdd rs ps csb mi KS0040 e_rd rw_wr d b 0 - d b 7 reset vss vcc a0 a1~a7 vma mpu (6800 -series) e r/w d0 - d7 reset gnd decoder gnd vcc resetb vcc figure 28. 6800-series mpu interface
65 com / 132 seg driver & controller for stn lcd ks00 40 55 clock s ynchronized s erial i nterfacing with any m icroprocessors vdd rs ps csb KS0040 scl(db6) mi si(db7) if reset vss vcc port4 port3 mpu port1 port0 reset gnd gnd vcc vcc or gnd resetb gnd figure 29. 4-pin serial interface
ks00 40 65 com / 132 seg driver & controller for stn lcd 56 lcd panel connection method (1/65 duty configuration) chip bottom & lower view (dirs = 0, dirc = 0) seg127 seg126 seg125 seg124 seg123 seg122 seg121 seg120 seg119 seg118 seg117 seg116 seg115 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 segi2 segi1 com56 ~ com49 com40 ~ com33 com24 ~ com17 com8 ~ com1 comi1 bottom view segi3 segi4 comi2 com64 ~ com57 com48 ~ com41 com32 ~ com25 com16 ~ com9 figure 30. chip bottom & lower view (dirs = 0, dirc = 0)
65 com / 132 seg driver & controller for stn lcd ks00 40 57 chip bottom & upper view (dirs = 1, dirc = 1) seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 com9 ~ com16 com25 ~ com32 com41 ~ com48 com57 ~ com64 comi2 segi4 segi3 bottom view comi1 com1 ~ com8 com17 ~ com24 com33 ~ com40 com49 ~ com56 segi1 segi2 figure 31. chip bottom & lower view (dirs = 1, dirc = 1)
ks00 40 65 com / 132 seg driver & controller for stn lcd 58 chip top & lower view (dirs = 1, dirc = 0) seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 segi3 segi4 comi2 com64 - com57 com48 - com41 com32 - com25 com16 - com9 top view segi2 segi1 com56 - com49 com40 - com33 com24 - com17 com8 - com1 comi1 figure 32. chip top & lower view (dirs = 1, dirc = 0)
65 com / 132 seg driver & controller for stn lcd ks00 40 59 chip top & upper view (dirs = 0, dirc = 1) seg127 seg126 seg125 seg124 seg123 seg122 seg121 seg120 seg119 seg118 seg117 seg116 seg115 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 comi1 com1 - com8 com17 - com24 com33 - com40 com49 - com56 segi1 segi2 top view com9 - com16 com25 - com32 com41 - com48 com57 - com64 comi2 segi4 segi3 figure 33. chip top & lower view (dirs = 0, dirc = 1)
ks00 40 65 com / 132 seg driver & controller for stn lcd 60 frame frequency 1/17 duty (dt1, dt0 = [0, 0]) 1-line selection period = 17 clock pulses one frame = 17 x 17 x 40.8 m s = 11.8 ms (1 clock=40.8 m s at fosc=24.5 khz ) frame frequency = 1 / 11.8 ms = 85 hz 17 16 ??? 2 1 v0 v1 v4 vs com1 1 frame 1-line selection period 1 frame 17 16 ??? 2 1 17 16 ??? 2 1 17 16 ??? 2 1 figure 34 . frame frequency (1/17 duty) 1/33 duty (dt1, dt0 = [0, 1]) v0 v1 v4 vs 1-line selection period = 17 clock pulses one frame = 17 x 33 x 21.0 m s = 11.8 ms (1 clock=21.0 m s at fosc=47.6 khz ) frame frequency = 1 / 11.8 ms = 85 hz com1 1 frame 1-line selection period 1 frame 30 31 32 33 ??? 4 3 2 1 30 31 32 33 ??? 4 3 2 1 figure 35 . frame frequency (1/33 duty)
65 com / 132 seg driver & controller for stn lcd ks00 40 61 1/49 duty (dt1, dt0 = [1, 0]) 49 48 ??? 2 1 v0 v1 v4 vs 1-line selection period = 17 clock pulses one frame = 17 x 49 x 14.2 m s = 11.8 ms (1 clock=14.2 m s at fosc=68.3 khz ) frame frequency = 1 / 11.8 ms = 85 hz com1 1 frame 1-line selection period 1 frame 49 48 ??? 2 1 49 48 ??? 2 1 49 48 ??? 2 1 figure 36 . frame frequency (1/49 duty) 1/65 duty (dt1, dt0 = [1, 1]) v0 v1 v4 vs 1-line selection period = 17 clock pulses one frame = 17 x 65 x 10.7 m s = 11.8 ms (1 clock=10.7 m s at fosc=93.7 khz ) frame frequency = 1 / 11.8 ms = 85 hz com1 1 frame 1-line selection period 1 frame 62 63 64 65 ??? 4 3 2 1 62 63 64 65 ??? 4 3 2 1 figure 37 . frame frequency (1/65 duty)
ks00 40 65 com / 132 seg driver & controller for stn lcd 62 table 24. duty select input & display window size dt1 dt0 duty display window size low low 1/17 1-line x 8-character low high 1/33 2-line x 8-character high low 1/49 3-line x 8-character high high 1/65 4-line x 8-character
65 com / 132 seg driver & controller for stn lcd ks00 40 63 maximum absolute rate table 25. absolute maximum ratings characteristics symbol value unit power supply voltage (1) v dd -0.3 to +7.0 v power supply voltage (2) v0, v out -0.3 to + 15 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +85 c storage temperature t stg -55 to +125 c note1: all the voltage levels are based on vss = 0v note2: voltage greater than above may damage to the circuit voltage level: v out 3 v0 3 vss. (v lcd = v0 - vss) voltage level: v0 3 v1 3 v2 3 v3 3 v4 3 v ss
ks00 40 65 com / 132 seg driver & controller for stn lcd 64 electrical characteristics dc characteristics table 26. dc characteristics (v dd = 2.4v to 3.6v, ta = -30 to +85 c ) item symbol condition min. typ. max. unit operating voltage v dd - 2.4 - 3.6 v i dd1 display operation (checker pattern) v0 = 9v without load no access from mpu - - 1 8 0 i dd2 sleep operation without load oscillator off - - 5 supply current (v dd = 3v, ta = 25 c ) i dd3 access operation from mpu fcyc = 200 khz - - 500 m a v ih - 0.8v dd - v dd input voltage v il - v ss - 0.2v dd v input leakage current i leak v in = 0v to v dd -1 - 1 m a r com io = 50 m a - - 5 r on resistance r seg io = 50 m a - - 10 k w frame frequency f fr v dd = 3v, ta = 25 c 60 85 110 hz display of 1 - line mode - 24.5 - display of 2 - line mode - 47.6 - display of 3 - line mode - 68.3 - external clock frequency f ck display of 4 - line mode - 93.7 - k hz voltage converter v dd 2 / 3 / 4 times v out ta = 25 c , c = 1 m f w ithout load 95 99 - % voltage regulator reference voltage v ref ta = 25 c, ref = l, vr pad ev value ( a ) = 63 w ithout load 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 ? v ss 4.0 - 13.0 v
65 com / 132 seg driver & controller for stn lcd ks 00 40 65 table 26. dc characteristics (continued) (v dd = 3.6v to 5.5v, ta = -30 to +85 c ) item symbol condition min typ max unit operating voltage v dd - 3.6 - 5.5 v i dd1 display operation (checker pattern) v0 = 9v without load no access from mpu - - 2 8 0 i dd2 sleep operation without load oscillator off - - 10 supply current (v dd = 5v, ta = 25 c ) i dd3 access operation from mpu fcyc = 200 khz - - 1000 m a v ih - 0.8v dd - v dd input voltage v il - v ss - 0.2v dd v input leakage current i leak v in = 0v to v dd -1 - 1 m a r com io = 50 m a - - 5 r on resistance r seg io = 50 m a - - 10 k w frame frequency f fr v dd = 5 v, ta = 25 c 60 85 110 hz display of 1 - line mode - 24.5 - display of 2 - line mode - 47.6 - display of 3 - line mode - 68.3 - external clock frequency f ck display of 4 - line mode - 93.7 - k hz *voltage converter v dd 2 / 3 times v out ta = 25 c , c = 1 m f w ithout load 95 99 - % voltage regulator reference voltage v ref ta = 25 c, ref = l, vr pad ev value ( a ) = 63 w ithout load 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 ? v ss 4.0 - 13.0 v note : when power supply (vdd) range is 3.6v to 5.5v, the 4 times boosting is not allowed.
ks00 40 65 com / 132 seg driver & controller for stn lcd 66 ac characteristics 6800-series mpu interface & write instruction table 27 . ac characteristics (6800-series write instruction) condition characteristic symbol min. typ. max. unit e cycle time t c 650 - pulse rise / fall time t r , t f - - 25 e pulse width high t wh 450 - - e pulse width low t wl 150 - - rs and csb setup time t su1 60 - - rs and csb hold time t h1 30 - - db setup time t su2 100 - - v dd = 2.4v to 3.6v, ta = -30 to +85 o c db hold time t h2 50 - - ns e cycle time t c 350 - pulse rise / fall time t r , t f - - 25 e pulse width high t wh 250 - - e pulse width low t wl 100 - - rs and csb setup time t su1 40 - - rs and csb hold time t h1 10 - - db setup time t su2 40 - - v dd = 3 . 6 v to 5 . 5 v, ta = -30 to +85 o c db hold time t h2 10 - - ns rs, csb db0 to db7 e_rd rw_wr t c t h2 t su2 t r t f t wl t wh t h1 t su1 figure 17. write bus mode timing (6800-series mpu interface)
65 com / 132 seg driver & controller for stn lcd ks00 40 67 8080-series mpu interface & write instruction table 28 . ac characteristics (8080-series write instruction) condition characteristic symbol min. typ. max. unit wr cycle time t c 650 - pulse rise / fall time t r , t f - - 25 wr pulse width high t wh 150 - - wr pulse width low t wl 450 - - rs and csb setup time t su1 60 - - rs and csb hold time t h1 30 - - db setup time t su2 100 - - v dd = 2.4v to 3.6v, ta = -30 to +85 o c db hold time t h2 50 - - ns wr cycle time t c 350 - pulse rise / fall time t r , t f - - 25 wr pulse width high t wh 100 - - wr pulse width low t wl 250 - - rs and csb setup time t su1 40 - - rs and csb hold time t h1 10 - - db setup time t su2 40 - - v dd = 3 . 6 v to 5 . 5 v, ta = -30 to +85 o c db hold time t h2 10 - - ns t r rs, csb db0 to db7 rw_wr t c t h2 t su2 t f t wh t wl t h1 t su1 figure 18. write bus mode timing (8080-series mpu interface)
ks00 40 65 com / 132 seg driver & controller for stn lcd 68 6800-series mpu interface & read instruction table 29 . ac characteristics (6800-series read instruction) condition characteristic symbol min. typ. max. unit e cycle time t c 650 - pulse rise / fall time t r , t f - - 25 e pulse width high t wh 450 - - e pulse width low t wl 150 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d - - 360 v dd = 2.4v to 3.6v, ta = -30 to +85 o c db output hold time t dh 2 0 - - ns e cycle time t c 350 - pulse rise / fall time t r , t f - - 25 e pulse width high t wh 250 - - e pulse width low t wl 100 - - rs and csb setup time t su 40 - - rs and csb hold time t h 10 - - db output delay time t d - - 120 v dd = 3 . 6 v to 5 . 5 v, ta = -30 to +85 o c db output hold time t dh 10 - - ns rs, csb db0 to db7 e_rd rw_wr t su t c t dh t d t f t r t h t wl t wh figure 19. read bus mode timing (6800-series mpu interface)
65 com / 132 seg driver & controller for stn lcd ks00 40 69 8080-series mpu interface & read instruction table 30 . ac characteristics (8080-series read instruction) condition characteristic symbol min. typ. max. unit rd cycle time t c 650 - pulse rise / fall time t r , t f - - 25 rd pulse width high t wh 150 - - rd pulse width low t wl 450 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d - 360 v dd = 2.4v to 3.6v, ta = -30 to +85 o c db output hold time t dh 2 0 - - ns rd cycle time t c 350 - pulse rise / fall time t r , t f - - 25 rd pulse width high t wh 100 - - rd pulse width low t wl 250 - - rs and csb setup time t su 40 - - rs and csb hold time t h 10 - - db output delay time t d - - 120 v dd = 3 . 6 v to 5 . 5 v, ta = -30 to +85 o c db output hold time t dh 10 - - ns t r rs, csb db0 to db7 e_rd t c t dh t d t f t wh t wl t h t su figure 20. read bus mode timing (8080-series mpu interface)
ks00 40 65 com / 132 seg driver & controller for stn lcd 70 clock synchronized serial mode table 31 . ac characteristics ( serial mode ) condition characteristic symbol min. typ. max. unit scl clock cycle time t c 1000 - pulse rise / fall time t r , t f - - 25 scl clock width (h / l) t w 300 - - csb setup time t su1 150 - - csb hold time t h1 700 - - rs data setup time t su2 50 - - rs data hold time t h2 300 - - si data setup time t su3 50 - - v dd = 2.4v to 3.6v, ta = -30 to +85 o c si data hold time t h3 50 - - ns scl clock cycle time t c 600 - pulse rise / fall time t r , t f - - 25 scl clock width (h / l) t w 200 - - csb setup time t su1 100 - - csb hold time t h1 400 - - rs data setup time t su2 40 - - rs data hold time t h2 200 - - si data setup time t su3 40 - - v dd = 3 . 6 v to 5 . 5 v, ta = -30 to +85 o c si data hold time t h3 40 - - ns csb si(db7) rs scl(db6) t h1 t h3 t h2 t c t su1 t su3 t su2 t w t w t f t r figure 32. clock synchronized serial interface mode timing diagram

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